1. Field of Invention
The present invention relates to a method of a fabricating metal-oxide-semiconductor (MOS) transistor. More particularly, the present invention relates to a method of fabricating a MOS transistor capable of increasing pad area size as well as improving alignment accuracy in subsequent processes.
2. Description of Related Art
A MOS transistor is a basic device in an integrated circuit. A MOS transistor unit comprises a gate structure, a source region and a drain region, wherein the gate structure includes a metallic layer and an oxide layer. In general, the metallic layer is made from a material having properties very close to silicon such as polysilicon, and the oxide layer is made from silicon dioxide (SiO.sub.2). The source/drain regions are formed in a substrate on either side of the gate structure.
The MOS transistor possesses n-type, p-type and complementary semiconductors, therefore, some doping processes are introduced to the MOS transistor. The implanted ions are called dopants. In the recent fabricating process for VLSI (Very Large Scaled Integrated) circuits, the main techniques for doping are, for example, a conventional method of diffusion or an advanced method of ion implantation. The method of diffusion depends on the mobility of dopants at high temperature, for example, about 800.degree. C. In the host of the semiconductor, the dopants are moved from a region with high concentration toward a region with low concentration to proceeding the doping treatment. The method of ion implantation is using ions as dopants that are implanted into the semiconductor device by promoting the energy of the ions.
The conventional methods for doping are proceeding at a high temperature. When the integration of the integrated circuits is increased, the accompaniment is that depth of a well in the devices and junction depth of the source region and the drain region are both decreased. However, the conventional methods for doping can not precisely control the distribution and profile of both the depth of the well and the junction depth. The ion implantation provides a preferred dopant profile and an advantage of easily controlling the concentration of implanted dopants. Therefore, the ion implantation is a main technique for doping in the modern fabricating method of VLSI devices.
FIGS. 1A-1C show cross-sectional views of forming a p-type metal oxide semiconductor transistor by a method of ion implantation. At first, referring to FIG. 1A, a gate structure 102 is formed over active area in the substrate 100. An implant treatment is performed over the substrate 100 by using, for example, the boron for doping. The gate structure 102 acts as a mask to prevent the boron from penetrating the substrate 100 in the active area. The concentration for the implantation is not higher than, for example, about 10.sup.13 atoms/cm.sup.2. The implanted region is so-called lightly doped drain (LDD) region 104. The LDD region 104 is used for prevent a short channel effect. The implant treatment is called P-implantation by those persons who skill in the art.
Owing to the ion implantation, bonding structures of a portion of the surface of the substrate 100 are damaged. Therefore, the substrate 100 is treated by an annealing process in a thermal diffusion furnace at about 900.degree. C. to 1000.degree. C., and the implanted borons are simultaneously diffused.
Next, a spacer 106 is formed around the sidewall of the gate structure 102, as shown in the FIG. 1B. A further P.sup.+ implant treatment is introduced on the substrate 100 by using the gate structure 102 and the spacer 106 as a mask and using, for example, the borons as dopants. The concentration for the implantation is high, for example, is about 10.sup.15 atoms/cm.sup.2 and the depth of the implantation is deep. A heavily doped drain region 104a is then formed beneath the LDD region 104. The substrate 100 is then treated again by an annealing and diffusion process, to repair the damaged surface of the substrate 100 and make the doped ions distributed well. The heavily doped drain region 104a is used for a main body of a source/drain region for further processing. The heavily doped drain region 104a is also used for avoid a leakage phenomenon in a following process of forming self-alignment silicide, owing to a characteristic of deeper region in the heavily doped drain region 104a.
The metal oxide semiconductor transistor formed by the conventional fabricating method has lightly doped drain regions (LDD), which can inhibit a short-channel effect and avoid a punchthrough phenomenon, which happens in the source/drain region of the semiconductor substrate, induced by applying a high voltage. The heavily doped drain region is necessary for a further process of salicidation. However, there are some restrictions in the conventional methods:
(1). For avoiding the short channel effect, the depth of the implanted ions is restricted to be very close to the surface of the semiconductor substrate while proceeding the lightly doping process. However, the controlling of the depth of the implantation is not easy. A profile of the distribution region of the implanted ions is easily changed while performing an annealing process and a thermal diffusion in the following process, that is, the profile is easily diffused and make the short channel effect happening again.
(2). It is uneasy to control a thermal budget, which is used for performing a p-type lightly doping process, for example, using BF.sub.2 or a N-halo process.
In light of the foregoing, there is a need to provide a relatively simple method of manufacturing high dielectric constant dielectric layer.